Recently, for the purpose of enhancing the throughput of a network, an optical interconnection in which data is transferred as an optical signal in optical fibers, has been introduced to the connection between processors in a multiprocessor system or the connection between a processor and a peripheral equipment such as a disk array. Furthermore, there have been many researches and proposals not only as to point-to-point interconnects but also as to a network for connecting of processors or peripheral equipments with switches.
For example, a network implemented with the Fibre Channel which is a typical optical interconnection standard for computers and an electrical switch called Fabric is described in ANSI X3T11, Fibre Channel Physical and Signaling Interface(FC-PH), Rev 4.3 (1994), pp.19-20.
A conventional optical network device comprises a large number network interface devices connected to processors and a switch device. The network interface includes a network interface control circuit, an optical transmitter, an optical receiver and a FIFO(first-in first-out) queue. The switch device includes an optical receiver, FIFO queues, an electrical switch and an optical transmitter.
Data output from the source network interface device is transmitted through the optical transmitter in the network interface device, the optical fiber, the optical receiver in the switch device, the FIFO queue, the electrical switch, the optical transmitter in the switch device, the optical fiber, the optical receiver in the network interface device and the FIFO queue, to the destination network interface device.
However, in the conventional optical network device, it takes a very long time to transmit data through the switch device, since the opto-electric conversion, serial-to-parallel conversion and decoding are conducted on the input side of the switch device and the encoding, parallel-to-serial conversion and electro-optic conversion are conducted on the output side of the switch device. It causes an increase in latency. In case of an optical network device where error detection and correction are conducted in the switch device, the latency is further increased.
Also, in case the throughput of a signal line is more than one Gbit/s, the number of parallel signal lines after the opto-electric conversion, serial-to-parallel conversion and decoding in the switch device is increased ten to hundred times that of serial signal lines. For example, when a signal line coded with 10B8B code with a throughput of 4 Gbit/s is serial-to-parallel converted down to the frequency of 100 MHz, at which the electric circuit of the switch device can be operated, the number of parallel signal lines becomes 32. In case of another electric circuit with a lower operating frequency, the number of signal lines will be further increased.
As an example, for a 16.times.16 switch composed of sixteen 4.times.4 element switches, the required number of signal lines of the input and output pins of the element switch is 256(=32.times.8). Including pins necessary for power supply and clock lines, the number is over 300. The number of signal lines of the input and output pins for 8.times.8 element switches is 512(=32.times.16). Including pins necessary for the power supply and clock lines, the number is over 600, Since an LSI package with input and output pins more than 500 is very expensive, the scale of an element switch that can be realized by a single LSI is at most 4.times.4. In general, a switch scale lager than 16.times.16, which is required for multiprocessors, must be realized by cascading element switch in multistages.
The switch scale of which is enlarged due to such a multistage composition causes a significant increase in latency. With a typical electrical circuit technology, three clocks are required for a signal to pass through an optical transmitter and an optical receiver, and five clocks are required to pass through a 4.times.4 element switch. Namely, at least 26(=3.times.2+5.times.4) clocks are required to pass a signal through such a 16.times.16 switch device. It therefore causes an increase in latency.
On the other hand, a multistage switch using a plurality of small scale switches is difficult to mount. In the example of the above 16.times.16 switch, required are sixteen 4.times.4 element switches, 1024(=32.times.16.times.2) switch inputs and outputs and 1536(=32.times.16.times.3) link wirings between the element switches.
Furthermore, in the conventional optical network device, since the switch device is asynchronously operated to the respective network interface devices, synchronizing process and asynchronous FIFO queues to adjust timing are needed. It therefore causes a further increase in latency.
Under these circumstances, to multiprocessor systems which are required not only of a high throughput but also of a reduced latency, such a switch device cannot bring a sufficient network performance, and the high-speed and broad-band characteristics of optical fibers cannot be sufficiently utilized therein. Namely, the improvement of the latency characteristic is desired.